15 #include <xtensa/corebits.h>
26 #define SYSTEM_EXCEPTION_MAP(XX) \
27 XX(ILLEGAL, GDB_SIGNAL_ILL, "Illegal Instruction") \
28 XX(SYSCALL, GDB_SIGNAL_USR2, "System Call") \
29 XX(INSTR_ERROR, GDB_SIGNAL_SEGV, "Instruction Fetch Error") \
30 XX(LOAD_STORE_ERROR, GDB_SIGNAL_SEGV, "Load Store Error") \
31 XX(LEVEL1_INTERRUPT, 0, "Level 1 Interrupt") \
32 XX(ALLOCA, 0, "MOVSP inst") \
33 XX(DIVIDE_BY_ZERO, GDB_SIGNAL_FPE, "Integer Divide by Zero") \
34 XX(SPECULATION, 0, "") \
35 XX(PRIVILEGED, GDB_SIGNAL_ABRT, "Privileged Instruction") \
36 XX(UNALIGNED, GDB_SIGNAL_EMT, "Unaligned Load/Store") \
39 XX(INSTR_DATA_ERROR, GDB_SIGNAL_EMT, "PIF Data Error on Instruction Fetch") \
40 XX(LOAD_STORE_DATA_ERROR, GDB_SIGNAL_EMT, "PIF Data Error on Load/Store") \
41 XX(INSTR_ADDR_ERROR, GDB_SIGNAL_EMT, "PIF Address Error on Instruction Fetch") \
42 XX(LOAD_STORE_ADDR_ERROR, GDB_SIGNAL_EMT, "PIF Address Error on Load/Store") \
43 XX(ITLB_MISS, 0, "ITLB Miss") \
44 XX(ITLB_MULTIHIT, 0, "ITLB Multihit") \
45 XX(INSTR_RING, 0, "Ring Privilege Violation on Instruction Fetch") \
47 XX(INSTR_PROHIBITED, GDB_SIGNAL_SEGV, "Cache Attribute does not allow Instruction Fetch") \
51 XX(DTLB_MISS, 0, "DTLB Miss") \
52 XX(DTLB_MULTIHIT, 0, "TBLD Multihit") \
53 XX(LOAD_STORE_RING, 0, "Ring Privilege Violation on Load/Store") \
55 XX(LOAD_PROHIBITED, GDB_SIGNAL_SEGV, "Cache Attribute does not allow Load") \
56 XX(STORE_PROHIBITED, GDB_SIGNAL_SEGV, "Cache Attribute does not allow Store")
58 #define EXCCAUSE_MAX EXCCAUSE_STORE_PROHIBITED