registers.h
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1 /****
2  * Sming Framework Project - Open Source framework for high efficiency native ESP8266 development.
3  * Created 2015 by Skurydin Alexey
4  * http://github.com/SmingHub/Sming
5  * All files of the Sming Core are provided under the LGPL v3 license.
6  *
7  * @author: 2019 - Mikee47 <mike@sillyhouse.net>
8  *
9  * GDB register definitions
10  *
11  ****/
12 
13 #pragma once
14 
15 #include "gdbstub-cfg.h"
16 #include "signals.h"
17 
18 #if GDBSTUB_GDB_PATCHED == 1
19 /*
20  * Patched GDB uses a small subset of registers
21  */
22 #define GDB_REGCOUNT 22
23 #define XT_REGISTER_MAP(XTREG) \
24  XX(0, a0) \
25  XX(1, a1) \
26  XX(2, a2) \
27  XX(3, a3) \
28  XX(4, a4) \
29  XX(5, a5) \
30  XX(6, a6) \
31  XX(7, a7) \
32  XX(8, a8) \
33  XX(9, a9) \
34  XX(10, a10) \
35  XX(11, a11) \
36  XX(12, a12) \
37  XX(13, a13) \
38  XX(14, a14) \
39  XX(15, a15) \
40  XX(16, pc) \
41  XX(17, sar) \
42  XX(18, litbase) \
43  XX(19, sr176) \
44  XX(20, sr208) \
45  XX(21, ps)
46 
47 #else
48 /*
49  * Unpatched GDB full register set
50  * Note that our stub doesn't return all of these, we send 'xxxxxxxx' for those
51  */
52 #define GDB_REGCOUNT 113
53 // This table is extracted from xtensa-config.c in GDB source code
54 #define XT_REGISTER_MAP(XX) \
55  XX(0, pc) \
56  XX(1, ar0) \
57  XX(2, ar1) \
58  XX(3, ar2) \
59  XX(4, ar3) \
60  XX(5, ar4) \
61  XX(6, ar5) \
62  XX(7, ar6) \
63  XX(8, ar7) \
64  XX(9, ar8) \
65  XX(10, ar9) \
66  XX(11, ar10) \
67  XX(12, ar11) \
68  XX(13, ar12) \
69  XX(14, ar13) \
70  XX(15, ar14) \
71  XX(16, ar15) \
72  XX(17, ar16) \
73  XX(18, ar17) \
74  XX(19, ar18) \
75  XX(20, ar19) \
76  XX(21, ar20) \
77  XX(22, ar21) \
78  XX(23, ar22) \
79  XX(24, ar23) \
80  XX(25, ar24) \
81  XX(26, ar25) \
82  XX(27, ar26) \
83  XX(28, ar27) \
84  XX(29, ar28) \
85  XX(30, ar29) \
86  XX(31, ar30) \
87  XX(32, ar31) \
88  XX(33, lbeg) \
89  XX(34, lend) \
90  XX(35, lcount) \
91  XX(36, sar) \
92  XX(37, litbase) \
93  XX(38, windowbase) \
94  XX(39, windowstart) \
95  XX(40, sr176) \
96  XX(41, sr208) \
97  XX(42, ps) \
98  XX(43, threadptr) \
99  XX(44, scompare1) \
100  XX(45, ptevaddr) \
101  XX(46, mmid) \
102  XX(47, rasid) \
103  XX(48, itlbcfg) \
104  XX(49, dtlbcfg) \
105  XX(50, ibreakenable) \
106  XX(51, ddr) \
107  XX(52, ibreaka0) \
108  XX(53, ibreaka1) \
109  XX(54, dbreaka0) \
110  XX(55, dbreaka1) \
111  XX(56, dbreakc0) \
112  XX(57, dbreakc1) \
113  XX(58, epc1) \
114  XX(59, epc2) \
115  XX(60, epc3) \
116  XX(61, epc4) \
117  XX(62, epc5) \
118  XX(63, epc6) \
119  XX(64, epc7) \
120  XX(65, depc) \
121  XX(66, eps2) \
122  XX(67, eps3) \
123  XX(68, eps4) \
124  XX(69, eps5) \
125  XX(70, eps6) \
126  XX(71, eps7) \
127  XX(72, excsave1) \
128  XX(73, excsave2) \
129  XX(74, excsave3) \
130  XX(75, excsave4) \
131  XX(76, excsave5) \
132  XX(77, excsave6) \
133  XX(78, excsave7) \
134  XX(79, cpenable) \
135  XX(80, interrupt) \
136  XX(81, intset) \
137  XX(82, intclear) \
138  XX(83, intenable) \
139  XX(84, vecbase) \
140  XX(85, exccause) \
141  XX(86, debugcause) \
142  XX(87, ccount) \
143  XX(88, prid) \
144  XX(89, icount) \
145  XX(90, icountlevel) \
146  XX(91, excvaddr) \
147  XX(92, ccompare0) \
148  XX(93, ccompare1) \
149  XX(94, ccompare2) \
150  XX(95, misc0) \
151  XX(96, misc1) \
152  XX(97, a0) \
153  XX(98, a1) \
154  XX(99, a2) \
155  XX(100, a3) \
156  XX(101, a4) \
157  XX(102, a5) \
158  XX(103, a6) \
159  XX(104, a7) \
160  XX(105, a8) \
161  XX(106, a9) \
162  XX(107, a10) \
163  XX(108, a11) \
164  XX(109, a12) \
165  XX(110, a13) \
166  XX(111, a14) \
167  XX(112, a15)
168 
169 #endif
170 
171 // Register numbers
172 enum GdbReg {
173 #define XX(idx, name) GdbReg_##name = idx,
175 #undef XX
176 };
GdbReg
Definition: registers.h:172
#define XX(idx, name)
Definition: registers.h:173
#define XT_REGISTER_MAP(XX)
Definition: registers.h:54