35 #define ESP8266_REG(addr) *((volatile uint32_t*)(0x60000000 + (addr))) 36 #define ESP8266_DREG(addr) *((volatile uint32_t*)(0x3FF00000 + (addr))) 37 #define ESP8266_CLOCK 80000000UL 40 #define CPU2X ESP8266_DREG(0x14) //when bit 0 is set, F_CPU = 160MHz 43 #define MAC0 ESP8266_DREG(0x50) 44 #define MAC1 ESP8266_DREG(0x54) 45 #define CHIPID ESP8266_DREG(0x58) 48 #define GPO ESP8266_REG(0x300) //GPIO_OUT R/W (Output Level) 49 #define GPOS ESP8266_REG(0x304) //GPIO_OUT_SET WO 50 #define GPOC ESP8266_REG(0x308) //GPIO_OUT_CLR WO 51 #define GPE ESP8266_REG(0x30C) //GPIO_ENABLE R/W (Enable) 52 #define GPES ESP8266_REG(0x310) //GPIO_ENABLE_SET WO 53 #define GPEC ESP8266_REG(0x314) //GPIO_ENABLE_CLR WO 54 #define GPI ESP8266_REG(0x318) //GPIO_IN RO (Read Input Level) 55 #define GPIE ESP8266_REG(0x31C) //GPIO_STATUS R/W (Interrupt Enable) 56 #define GPIES ESP8266_REG(0x320) //GPIO_STATUS_SET WO 57 #define GPIEC ESP8266_REG(0x324) //GPIO_STATUS_CLR WO 59 #define GPOP(p) ((GPO & (1 << ((p)&0xF))) != 0) 60 #define GPEP(p) ((GPE & (1 << ((p)&0xF))) != 0) 61 #define GPIP(p) ((GPI & (1 << ((p)&0xF))) != 0) 62 #define GPIEP(p) ((GPIE & (1 << ((p)&0xF))) != 0) 65 #define GPC(p) ESP8266_REG(0x328 + ((p & 0xF) * 4)) 66 #define GPC0 ESP8266_REG(0x328) //GPIO_PIN0 67 #define GPC1 ESP8266_REG(0x32C) //GPIO_PIN1 68 #define GPC2 ESP8266_REG(0x330) //GPIO_PIN2 69 #define GPC3 ESP8266_REG(0x334) //GPIO_PIN3 70 #define GPC4 ESP8266_REG(0x338) //GPIO_PIN4 71 #define GPC5 ESP8266_REG(0x33C) //GPIO_PIN5 72 #define GPC6 ESP8266_REG(0x340) //GPIO_PIN6 73 #define GPC7 ESP8266_REG(0x344) //GPIO_PIN7 74 #define GPC8 ESP8266_REG(0x348) //GPIO_PIN8 75 #define GPC9 ESP8266_REG(0x34C) //GPIO_PIN9 76 #define GPC10 ESP8266_REG(0x350) //GPIO_PIN10 77 #define GPC11 ESP8266_REG(0x354) //GPIO_PIN11 78 #define GPC12 ESP8266_REG(0x358) //GPIO_PIN12 79 #define GPC13 ESP8266_REG(0x35C) //GPIO_PIN13 80 #define GPC14 ESP8266_REG(0x360) //GPIO_PIN14 81 #define GPC15 ESP8266_REG(0x364) //GPIO_PIN15 84 #define GPCWE 10 //WAKEUP_ENABLE (can be 1 only when INT_TYPE is high or low) 85 #define GPCI 7 //INT_TYPE (3bits) 0:disable,1:rising,2:falling,3:change,4:low,5:high 86 #define GPCD 2 //DRIVER 0:normal,1:open drain 87 #define GPCS 0 //SOURCE 0:GPIO_DATA,1:SigmaDelta 89 #define GPMUX ESP8266_REG(0x800) 91 #define GPF0 ESP8266_REG(0x834) 92 #define GPF1 ESP8266_REG(0x818) 93 #define GPF2 ESP8266_REG(0x838) 94 #define GPF3 ESP8266_REG(0x814) 95 #define GPF4 ESP8266_REG(0x83C) 96 #define GPF5 ESP8266_REG(0x840) 97 #define GPF6 ESP8266_REG(0x81C) 98 #define GPF7 ESP8266_REG(0x820) 99 #define GPF8 ESP8266_REG(0x824) 100 #define GPF9 ESP8266_REG(0x828) 101 #define GPF10 ESP8266_REG(0x82C) 102 #define GPF11 ESP8266_REG(0x830) 103 #define GPF12 ESP8266_REG(0x804) 104 #define GPF13 ESP8266_REG(0x808) 105 #define GPF14 ESP8266_REG(0x80C) 106 #define GPF15 ESP8266_REG(0x810) 109 #define GPF(p) ESP8266_REG(0x800 + esp8266_gpioToFn[(p & 0xF)]) 112 #define GPFSOE 0 //Sleep OE 113 #define GPFSS 1 //Sleep Sel 114 #define GPFSPD 2 //Sleep Pulldown 115 #define GPFSPU 3 //Sleep Pullup 116 #define GPFFS0 4 //Function Select bit 0 117 #define GPFFS1 5 //Function Select bit 1 118 #define GPFPD 6 //Pulldown 119 #define GPFPU 7 //Pullup 120 #define GPFFS2 8 //Function Select bit 2 121 #define GPFFS(f) (((((f)&4) != 0) << GPFFS2) | ((((f)&2) != 0) << GPFFS1) | ((((f)&1) != 0) << GPFFS0)) 122 #define GPFFS_GPIO(p) (((p) == 0 || (p) == 2 || (p) == 4 || (p) == 5) ? 0 : ((p) == 16) ? 1 : 3) 123 #define GPFFS_BUS(p) \ 124 (((p) == 1 || (p) == 3) ? 0 \ 125 : ((p) == 2 || (p) == 12 || (p) == 13 || (p) == 14 || (p) == 15) ? 2 : ((p) == 0) ? 4 : 1) 128 #define GP16O ESP8266_REG(0x768) 129 #define GP16E ESP8266_REG(0x774) 130 #define GP16I ESP8266_REG(0x78C) 133 #define GP16C ESP8266_REG(0x790) 137 #define GP16F ESP8266_REG(0x7A0) 141 #define GP16FFS0 0 //Function Select bit 0 142 #define GP16FFS1 1 //Function Select bit 1 143 #define GP16FPD 3 //Pulldown 144 #define GP16FSPD 5 //Sleep Pulldown 145 #define GP16FFS2 6 //Function Select bit 2 146 #define GP16FFS(f) (((f)&0x03) | (((f)&0x04) << 4)) 149 #define T1L ESP8266_REG(0x600) //Load Value (Starting Value of Counter) 23bit (0-8388607) 150 #define T1V ESP8266_REG(0x604) //(RO) Current Value 151 #define T1C ESP8266_REG(0x608) //Control Register 152 #define T1I ESP8266_REG(0x60C) //Interrupt Status Register (1bit) write to clear 154 #define TEIE ESP8266_DREG(0x04) 155 #define TEIE1 0x02 //bit for timer 1 158 #define T2L ESP8266_REG(0x620) //Load Value (Starting Value of Counter) 159 #define T2V ESP8266_REG(0x624) //(RO) Current Value 160 #define T2C ESP8266_REG(0x628) //Control Register 161 #define T2I ESP8266_REG(0x62C) //Interrupt Status Register (1bit) write to clear 162 #define T2A ESP8266_REG(0x630) //Alarm Value 165 #define TCIS 8 //Interrupt Status 166 #define TCTE 7 //Timer Enable 167 #define TCAR 6 //AutoReload (restart timer when condition is reached) 168 #define TCPD 2 //Prescale Devider (2bit) 0:1(12.5ns/tick), 1:16(0.2us/tick), 2/3:256(3.2us/tick) 169 #define TCIT 0 //Interrupt Type 0:edge, 1:level 172 #define RTCSV ESP8266_REG(0x704) //RTC SLEEP COUNTER Target Value 173 #define RTCCV ESP8266_REG(0x71C) //RTC SLEEP COUNTER Value 174 #define RTCIS ESP8266_REG(0x720) //RTC INT Status 175 #define RTCIC ESP8266_REG(0x724) //RTC INT Clear 176 #define RTCIE ESP8266_REG(0x728) //RTC INT Enable 178 #define RTC_USER_MEM ((volatile uint32_t*)0x60001200) 181 #define IOSWAP ESP8266_DREG(0x28) 182 #define IOSWAPU 0 //Swaps UART 183 #define IOSWAPS 1 //Swaps SPI 184 #define IOSWAPU0 2 //Swaps UART 0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts) 185 #define IOSWAPU1 3 //Swaps UART 1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts) 186 #define IOSWAPHS 5 //Sets HSPI with higher prio 187 #define IOSWAP2HS 6 //Sets Two SPI Masters on HSPI 188 #define IOSWAP2CS 7 //Sets Two SPI Masters on CSPI 191 #define UIS ESP8266_DREG(0x20020) 196 #define U0F ESP8266_REG(0x000) //UART FIFO 197 #define U0IR ESP8266_REG(0x004) //INT_RAW 198 #define U0IS ESP8266_REG(0x008) //INT_STATUS 199 #define U0IE ESP8266_REG(0x00c) //INT_ENABLE 200 #define U0IC ESP8266_REG(0x010) //INT_CLEAR 201 #define U0D ESP8266_REG(0x014) //CLKDIV 202 #define U0A ESP8266_REG(0x018) //AUTOBAUD 203 #define U0S ESP8266_REG(0x01C) //STATUS 204 #define U0C0 ESP8266_REG(0x020) //CONF0 205 #define U0C1 ESP8266_REG(0x024) //CONF1 206 #define U0LP ESP8266_REG(0x028) //LOW_PULSE 207 #define U0HP ESP8266_REG(0x02C) //HIGH_PULSE 208 #define U0PN ESP8266_REG(0x030) //PULSE_NUM 209 #define U0DT ESP8266_REG(0x078) //DATE 210 #define U0ID ESP8266_REG(0x07C) //ID 213 #define U1F ESP8266_REG(0xF00) //UART FIFO 214 #define U1IR ESP8266_REG(0xF04) //INT_RAW 215 #define U1IS ESP8266_REG(0xF08) //INT_STATUS 216 #define U1IE ESP8266_REG(0xF0c) //INT_ENABLE 217 #define U1IC ESP8266_REG(0xF10) //INT_CLEAR 218 #define U1D ESP8266_REG(0xF14) //CLKDIV 219 #define U1A ESP8266_REG(0xF18) //AUTOBAUD 220 #define U1S ESP8266_REG(0xF1C) //STATUS 221 #define U1C0 ESP8266_REG(0xF20) //CONF0 222 #define U1C1 ESP8266_REG(0xF24) //CONF1 223 #define U1LP ESP8266_REG(0xF28) //LOW_PULSE 224 #define U1HP ESP8266_REG(0xF2C) //HIGH_PULSE 225 #define U1PN ESP8266_REG(0xF30) //PULSE_NUM 226 #define U1DT ESP8266_REG(0xF78) //DATE 227 #define U1ID ESP8266_REG(0xF7C) //ID 230 #define USF(u) ESP8266_REG(0x000 + (0xF00 * (u & 1))) //UART FIFO 231 #define USIR(u) ESP8266_REG(0x004 + (0xF00 * (u & 1))) //INT_RAW 232 #define USIS(u) ESP8266_REG(0x008 + (0xF00 * (u & 1))) //INT_STATUS 233 #define USIE(u) ESP8266_REG(0x00c + (0xF00 * (u & 1))) //INT_ENABLE 234 #define USIC(u) ESP8266_REG(0x010 + (0xF00 * (u & 1))) //INT_CLEAR 235 #define USD(u) ESP8266_REG(0x014 + (0xF00 * (u & 1))) //CLKDIV 236 #define USA(u) ESP8266_REG(0x018 + (0xF00 * (u & 1))) //AUTOBAUD 237 #define USS(u) ESP8266_REG(0x01C + (0xF00 * (u & 1))) //STATUS 238 #define USC0(u) ESP8266_REG(0x020 + (0xF00 * (u & 1))) //CONF0 239 #define USC1(u) ESP8266_REG(0x024 + (0xF00 * (u & 1))) //CONF1 240 #define USLP(u) ESP8266_REG(0x028 + (0xF00 * (u & 1))) //LOW_PULSE 241 #define USHP(u) ESP8266_REG(0x02C + (0xF00 * (u & 1))) //HIGH_PULSE 242 #define USPN(u) ESP8266_REG(0x030 + (0xF00 * (u & 1))) //PULSE_NUM 243 #define USDT(u) ESP8266_REG(0x078 + (0xF00 * (u & 1))) //DATE 244 #define USID(u) ESP8266_REG(0x07C + (0xF00 * (u & 1))) //ID 247 #define UITO 8 //RX FIFO TimeOut 248 #define UIBD 7 //Break Detected 249 #define UICTS 6 //CTS Changed 250 #define UIDSR 5 //DSR Change 251 #define UIOF 4 //RX FIFO OverFlow 252 #define UIFR 3 //Frame Error 253 #define UIPE 2 //Parity Error 254 #define UIFE 1 //TX FIFO Empty 255 #define UIFF 0 //RX FIFO Full 258 #define USTX 31 //TX PIN Level 259 #define USRTS 30 //RTS PIN Level 260 #define USDTR 39 //DTR PIN Level 261 #define USTXC 16 //TX FIFO COUNT (8bit) 262 #define USRXD 15 //RX PIN Level 263 #define USCTS 14 //CTS PIN Level 264 #define USDSR 13 //DSR PIN Level 265 #define USRXC 0 //RX FIFO COUNT (8bit) 268 #define UCDTRI 24 //Invert DTR 269 #define UCRTSI 23 //Invert RTS 270 #define UCTXI 22 //Invert TX 271 #define UCDSRI 21 //Invert DSR 272 #define UCCTSI 20 //Invert CTS 273 #define UCRXI 19 //Invert RX 274 #define UCTXRST 18 //Reset TX FIFO 275 #define UCRXRST 17 //Reset RX FIFO 276 #define UCTXHFE 15 //TX Harware Flow Enable 277 #define UCLBE 14 //LoopBack Enable 278 #define UCBRK 8 //Send Break on the TX line 279 #define UCSWDTR 7 //Set this bit to assert DTR 280 #define UCSWRTS 6 //Set this bit to assert RTS 281 #define UCSBN 4 //StopBits Count (2bit) 0:disable, 1:1bit, 2:1.5bit, 3:2bit 282 #define UCBN 2 //DataBits Count (2bin) 0:5bit, 1:6bit, 2:7bit, 3:8bit 283 #define UCPAE 1 //Parity Enable 284 #define UCPA 0 //Parity 0:even, 1:odd 287 #define UCTOE 31 //RX TimeOut Enable 288 #define UCTOT 24 //RX TimeOut Treshold (7bit) 289 #define UCRXHFE 23 //RX Harware Flow Enable 290 #define UCRXHFT 16 //RX Harware Flow Treshold (7bit) 291 #define UCFET 8 //TX FIFO Empty Treshold (7bit) 292 #define UCFFT 0 //RX FIFO Full Treshold (7bit) 295 #define SPIRDY ESP8266_DREG(0x0C) 296 #define SPI_BUSY 9 //wait SPI idle 299 #define SPI0CMD ESP8266_REG(0x200) 300 #define SPI0A ESP8266_REG(0x204) 301 #define SPI0C ESP8266_REG(0x208) 302 #define SPI0C1 ESP8266_REG(0x20C) 303 #define SPI0RS ESP8266_REG(0x210) 304 #define SPI0C2 ESP8266_REG(0x214) 305 #define SPI0CLK ESP8266_REG(0x218) 306 #define SPI0U ESP8266_REG(0x21C) 307 #define SPI0U1 ESP8266_REG(0x220) 308 #define SPI0U2 ESP8266_REG(0x224) 309 #define SPI0WS ESP8266_REG(0x228) 310 #define SPI0P ESP8266_REG(0x22C) 311 #define SPI0S ESP8266_REG(0x230) 312 #define SPI0S1 ESP8266_REG(0x234) 313 #define SPI0S2 ESP8266_REG(0x238) 314 #define SPI0S3 ESP8266_REG(0x23C) 315 #define SPI0W0 ESP8266_REG(0x240) 316 #define SPI0W1 ESP8266_REG(0x244) 317 #define SPI0W2 ESP8266_REG(0x248) 318 #define SPI0W3 ESP8266_REG(0x24C) 319 #define SPI0W4 ESP8266_REG(0x250) 320 #define SPI0W5 ESP8266_REG(0x254) 321 #define SPI0W6 ESP8266_REG(0x258) 322 #define SPI0W7 ESP8266_REG(0x25C) 323 #define SPI0W8 ESP8266_REG(0x260) 324 #define SPI0W9 ESP8266_REG(0x264) 325 #define SPI0W10 ESP8266_REG(0x268) 326 #define SPI0W11 ESP8266_REG(0x26C) 327 #define SPI0W12 ESP8266_REG(0x270) 328 #define SPI0W13 ESP8266_REG(0x274) 329 #define SPI0W14 ESP8266_REG(0x278) 330 #define SPI0W15 ESP8266_REG(0x27C) 331 #define SPI0E3 ESP8266_REG(0x2FC) 332 #define SPI0W(p) ESP8266_REG(0x240 + ((p & 0xF) * 4)) 335 #define SPI1CMD ESP8266_REG(0x100) 336 #define SPI1A ESP8266_REG(0x104) 337 #define SPI1C ESP8266_REG(0x108) 338 #define SPI1C1 ESP8266_REG(0x10C) 339 #define SPI1RS ESP8266_REG(0x110) 340 #define SPI1C2 ESP8266_REG(0x114) 341 #define SPI1CLK ESP8266_REG(0x118) 342 #define SPI1U ESP8266_REG(0x11C) 343 #define SPI1U1 ESP8266_REG(0x120) 344 #define SPI1U2 ESP8266_REG(0x124) 345 #define SPI1WS ESP8266_REG(0x128) 346 #define SPI1P ESP8266_REG(0x12C) 347 #define SPI1S ESP8266_REG(0x130) 348 #define SPI1S1 ESP8266_REG(0x134) 349 #define SPI1S2 ESP8266_REG(0x138) 350 #define SPI1S3 ESP8266_REG(0x13C) 351 #define SPI1W0 ESP8266_REG(0x140) 352 #define SPI1W1 ESP8266_REG(0x144) 353 #define SPI1W2 ESP8266_REG(0x148) 354 #define SPI1W3 ESP8266_REG(0x14C) 355 #define SPI1W4 ESP8266_REG(0x150) 356 #define SPI1W5 ESP8266_REG(0x154) 357 #define SPI1W6 ESP8266_REG(0x158) 358 #define SPI1W7 ESP8266_REG(0x15C) 359 #define SPI1W8 ESP8266_REG(0x160) 360 #define SPI1W9 ESP8266_REG(0x164) 361 #define SPI1W10 ESP8266_REG(0x168) 362 #define SPI1W11 ESP8266_REG(0x16C) 363 #define SPI1W12 ESP8266_REG(0x170) 364 #define SPI1W13 ESP8266_REG(0x174) 365 #define SPI1W14 ESP8266_REG(0x178) 366 #define SPI1W15 ESP8266_REG(0x17C) 367 #define SPI1E0 ESP8266_REG(0x1F0) 368 #define SPI1E1 ESP8266_REG(0x1F4) 369 #define SPI1E2 ESP8266_REG(0x1F8) 370 #define SPI1E3 ESP8266_REG(0x1FC) 371 #define SPI1W(p) ESP8266_REG(0x140 + ((p & 0xF) * 4)) 374 #define SPIIR ESP8266_DREG(0x20) 375 #define SPII0 4 //SPI0 Interrupt 376 #define SPII1 7 //SPI1 Interrupt 377 #define SPII2 9 //I2S Interrupt 380 #define SPICMDREAD (1 << 31) //SPI_FLASH_READ 381 #define SPICMDWREN (1 << 30) //SPI_FLASH_WREN 382 #define SPICMDWRDI (1 << 29) //SPI_FLASH_WRDI 383 #define SPICMDRDID (1 << 28) //SPI_FLASH_RDID 384 #define SPICMDRDSR (1 << 27) //SPI_FLASH_RDSR 385 #define SPICMDWRSR (1 << 26) //SPI_FLASH_WRSR 386 #define SPICMDPP (1 << 25) //SPI_FLASH_PP 387 #define SPICMDSE (1 << 24) //SPI_FLASH_SE 388 #define SPICMDBE (1 << 23) //SPI_FLASH_BE 389 #define SPICMDCE (1 << 22) //SPI_FLASH_CE 390 #define SPICMDDP (1 << 21) //SPI_FLASH_DP 391 #define SPICMDRES (1 << 20) //SPI_FLASH_RES 392 #define SPICMDHPM (1 << 19) //SPI_FLASH_HPM 393 #define SPICMDUSR (1 << 18) //SPI_FLASH_USR 394 #define SPIBUSY (1 << 18) //SPI_USR 397 #define SPICWBO (1 << 26) //SPI_WR_BIT_ODER 398 #define SPICRBO (1 << 25) //SPI_RD_BIT_ODER 399 #define SPICQIO (1 << 24) //SPI_QIO_MODE 400 #define SPICDIO (1 << 23) //SPI_DIO_MODE 401 #define SPIC2BSE (1 << 22) //SPI_TWO_BYTE_STATUS_EN 402 #define SPICWPR (1 << 21) //SPI_WP_REG 403 #define SPICQOUT (1 << 20) //SPI_QOUT_MODE 404 #define SPICSHARE (1 << 19) //SPI_SHARE_BUS 405 #define SPICHOLD (1 << 18) //SPI_HOLD_MODE 406 #define SPICAHB (1 << 17) //SPI_ENABLE_AHB 407 #define SPICSSTAAI (1 << 16) //SPI_SST_AAI 408 #define SPICRESANDRES (1 << 15) //SPI_RESANDRES 409 #define SPICDOUT (1 << 14) //SPI_DOUT_MODE 410 #define SPICFASTRD (1 << 13) //SPI_FASTRD_MODE 413 #define SPIC1TCSH 0xF //SPI_T_CSH 414 #define SPIC1TCSH_S 28 //SPI_T_CSH_S 415 #define SPIC1TRES 0xFFF //SPI_T_RES 416 #define SPIC1TRES_S 16 //SPI_T_RES_S 417 #define SPIC1BTL 0xFFFF //SPI_BUS_TIMER_LIMIT 418 #define SPIC1BTL_S 0 //SPI_BUS_TIMER_LIMIT_S 421 #define SPIRSEXT 0xFF //SPI_STATUS_EXT 422 #define SPIRSEXT_S 24 //SPI_STATUS_EXT_S 423 #define SPIRSWB 0xFF //SPI_WB_MODE 424 #define SPIRSWB_S 16 //SPI_WB_MODE_S 425 #define SPIRSSP (1 << 7) //SPI_FLASH_STATUS_PRO_FLAG 426 #define SPIRSTBP (1 << 5) //SPI_FLASH_TOP_BOT_PRO_FLAG 427 #define SPIRSBP2 (1 << 4) //SPI_FLASH_BP2 428 #define SPIRSBP1 (1 << 3) //SPI_FLASH_BP1 429 #define SPIRSBP0 (1 << 2) //SPI_FLASH_BP0 430 #define SPIRSWRE (1 << 1) //SPI_FLASH_WRENABLE_FLAG 431 #define SPIRSBUSY (1 << 0) //SPI_FLASH_BUSY_FLAG 434 #define SPIC2CSDN 0xF //SPI_CS_DELAY_NUM 435 #define SPIC2CSDN_S 28 //SPI_CS_DELAY_NUM_S 436 #define SPIC2CSDM 0x3 //SPI_CS_DELAY_MODE 437 #define SPIC2CSDM_S 26 //SPI_CS_DELAY_MODE_S 438 #define SPIC2MOSIDN 0x7 //SPI_MOSI_DELAY_NUM 439 #define SPIC2MOSIDN_S 23 //SPI_MOSI_DELAY_NUM_S 440 #define SPIC2MOSIDM 0x3 //SPI_MOSI_DELAY_MODE 441 #define SPIC2MOSIDM_S 21 //SPI_MOSI_DELAY_MODE_S 442 #define SPIC2MISODN 0x7 //SPI_MISO_DELAY_NUM 443 #define SPIC2MISODN_S 18 //SPI_MISO_DELAY_NUM_S 444 #define SPIC2MISODM 0x3 //SPI_MISO_DELAY_MODE 445 #define SPIC2MISODM_S 16 //SPI_MISO_DELAY_MODE_S 446 #define SPIC2CKOHM 0xF //SPI_CK_OUT_HIGH_MODE 447 #define SPIC2CKOHM_S 12 //SPI_CK_OUT_HIGH_MODE_S 448 #define SPIC2CKOLM 0xF //SPI_CK_OUT_LOW_MODE 449 #define SPIC2CKOLM_S 8 //SPI_CK_OUT_LOW_MODE_S 450 #define SPIC2HT 0xF //SPI_HOLD_TIME 451 #define SPIC2HT_S 4 //SPI_HOLD_TIME_S 452 #define SPIC2ST 0xF //SPI_SETUP_TIME 453 #define SPIC2ST_S 0 //SPI_SETUP_TIME_S 456 #define SPICLK_EQU_SYSCLK (1 << 31) //SPI_CLK_EQU_SYSCLK 457 #define SPICLKDIVPRE 0x1FFF //SPI_CLKDIV_PRE 458 #define SPICLKDIVPRE_S 18 //SPI_CLKDIV_PRE_S 459 #define SPICLKCN 0x3F //SPI_CLKCNT_N 460 #define SPICLKCN_S 12 //SPI_CLKCNT_N_S 461 #define SPICLKCH 0x3F //SPI_CLKCNT_H 462 #define SPICLKCH_S 6 //SPI_CLKCNT_H_S 463 #define SPICLKCL 0x3F //SPI_CLKCNT_L 464 #define SPICLKCL_S 0 //SPI_CLKCNT_L_S 467 #define SPIUCOMMAND (1 << 31) //COMMAND pahse, SPI_USR_COMMAND 468 #define SPIUADDR (1 << 30) //ADDRESS phase, SPI_FLASH_USR_ADDR 469 #define SPIUDUMMY (1 << 29) //DUMMY phase, SPI_FLASH_USR_DUMMY 470 #define SPIUMISO (1 << 28) //MISO phase, SPI_FLASH_USR_DIN 471 #define SPIUMOSI (1 << 27) //MOSI phase, SPI_FLASH_DOUT 472 #define SPIUDUMMYIDLE (1 << 26) //SPI_USR_DUMMY_IDLE 473 #define SPIUMOSIH (1 << 25) //MOSI phase uses W8-W15, SPI_USR_DOUT_HIGHPART 474 #define SPIUMISOH (1 << 24) //MISO pahse uses W8-W15, SPI_USR_DIN_HIGHPART 475 #define SPIUPREPHOLD (1 << 23) //SPI_USR_PREP_HOLD 476 #define SPIUCMDHOLD (1 << 22) //SPI_USR_CMD_HOLD 477 #define SPIUADDRHOLD (1 << 21) //SPI_USR_ADDR_HOLD 478 #define SPIUDUMMYHOLD (1 << 20) //SPI_USR_DUMMY_HOLD 479 #define SPIUMISOHOLD (1 << 19) //SPI_USR_DIN_HOLD 480 #define SPIUMOSIHOLD (1 << 18) //SPI_USR_DOUT_HOLD 481 #define SPIUHOLDPOL (1 << 17) //SPI_USR_HOLD_POL 482 #define SPIUSIO (1 << 16) //SPI_SIO 483 #define SPIUFWQIO (1 << 15) //SPI_FWRITE_QIO 484 #define SPIUFWDIO (1 << 14) //SPI_FWRITE_DIO 485 #define SPIUFWQUAD (1 << 13) //SPI_FWRITE_QUAD 486 #define SPIUFWDUAL (1 << 12) //SPI_FWRITE_DUAL 487 #define SPIUWRBYO (1 << 11) //SPI_WR_BYTE_ORDER 488 #define SPIURDBYO (1 << 10) //SPI_RD_BYTE_ORDER 489 #define SPIUAHBEM 0x3 //SPI_AHB_ENDIAN_MODE 490 #define SPIUAHBEM_S 8 //SPI_AHB_ENDIAN_MODE_S 491 #define SPIUSME (1 << 7) //SPI Master Edge (0:falling, 1:rising), SPI_CK_OUT_EDGE 492 #define SPIUSSE (1 << 6) //SPI Slave Edge (0:falling, 1:rising), SPI_CK_I_EDGE 493 #define SPIUCSSETUP (1 << 5) //SPI_CS_SETUP 494 #define SPIUCSHOLD (1 << 4) //SPI_CS_HOLD 495 #define SPIUAHBUCMD (1 << 3) //SPI_AHB_USR_COMMAND 496 #define SPIUAHBUCMD4B (1 << 1) //SPI_AHB_USR_COMMAND_4BYTE 497 #define SPIUDUPLEX (1 << 0) //SPI_DOUTDIN 500 #define SPILCOMMAND 28 //4 bit in SPIxU2 default 7 (8bit) 501 #define SPILADDR 26 //6 bit in SPIxU1 default:23 (24bit) 502 #define SPILDUMMY 0 //8 bit in SPIxU1 default:0 (0 cycles) 503 #define SPILMISO 8 //9 bit in SPIxU1 default:0 (1bit) 504 #define SPILMOSI 17 //9 bit in SPIxU1 default:0 (1bit) 506 #define SPIMCOMMAND 0xF 507 #define SPIMADDR 0x3F 508 #define SPIMDUMMY 0xFF 509 #define SPIMMISO 0x1FF 510 #define SPIMMOSI 0x1FF 513 #define SPISSRES (1 << 31) //SYNC RESET, SPI_SYNC_RESET 514 #define SPISE (1 << 30) //Slave Enable, SPI_SLAVE_MODE 515 #define SPISBE (1 << 29) //WR/RD BUF enable, SPI_SLV_WR_RD_BUF_EN 516 #define SPISSE (1 << 28) //STA enable, SPI_SLV_WR_RD_STA_EN 517 #define SPISCD (1 << 27) //CMD define, SPI_SLV_CMD_DEFINE 518 #define SPISTRCNT 0xF //SPI_TRANS_CNT 519 #define SPISTRCNT_S 23 //SPI_TRANS_CNT_S 520 #define SPISSLS 0x7 //SPI_SLV_LAST_STATE 521 #define SPISSLS_S 20 //SPI_SLV_LAST_STATE_S 522 #define SPISSLC 0x7 //SPI_SLV_LAST_COMMAND 523 #define SPISSLC_S 17 //SPI_SLV_LAST_COMMAND_S 524 #define SPISCSIM 0x3 //SPI_CS_I_MODE 525 #define SPIDCSIM_S 10 //SPI_CS_I_MODE_S 526 #define SPISTRIE (1 << 9) //TRANS interrupt enable 527 #define SPISWSIE (1 << 8) //WR_STA interrupt enable 528 #define SPISRSIE (1 << 7) //RD_STA interrupt enable 529 #define SPISWBIE (1 << 6) //WR_BUF interrupt enable 530 #define SPISRBIE (1 << 5) //RD_BUF interrupt enable 531 #define SPISTRIS (1 << 4) //TRANS interrupt status 532 #define SPISWSIS (1 << 3) //WR_STA interrupt status 533 #define SPISRSIS (1 << 2) //RD_STA interrupt status 534 #define SPISWBIS (1 << 1) //WR_BUF interrupt status 535 #define SPISRBIS (1 << 0) //RD_BUF interrupt status 538 #define SPIS1LSTA 27 //5 bit in SPIxS1 default:0 (1bit), SPI_SLV_STATUS_BITLEN 539 #define SPIS1FE (1 << 26) //SPI_SLV_STATUS_FAST_EN 540 #define SPIS1RSTA (1 << 25) //default:0 enable STA read from Master, SPI_SLV_STATUS_READBACK 541 #define SPIS1LBUF 16 //9 bit in SPIxS1 default:0 (1bit), SPI_SLV_BUF_BITLEN 542 #define SPIS1LRBA 10 //6 bit in SPIxS1 default:0 (1bit), SPI_SLV_RD_ADDR_BITLEN 543 #define SPIS1LWBA 4 //6 bit in SPIxS1 default:0 (1bit), SPI_SLV_WR_ADDR_BITLEN 544 #define SPIS1WSDE (1 << 3) //SPI_SLV_WRSTA_DUMMY_EN 545 #define SPIS1RSDE (1 << 2) //SPI_SLV_RDSTA_DUMMY_EN 546 #define SPIS1WBDE (1 << 1) //SPI_SLV_WRBUF_DUMMY_EN 547 #define SPIS1RBDE (1 << 0) //SPI_SLV_RDBUF_DUMMY_EN 550 #define SPIS2WBDL 0xFF //SPI_SLV_WRBUF_DUMMY_CYCLELEN 551 #define SPIS2WBDL_S 24 //SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 552 #define SPIS2RBDL 0xFF //SPI_SLV_RDBUF_DUMMY_CYCLELEN 553 #define SPIS2RBDL_S 16 //SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 554 #define SPIS2WSDL 0xFF //SPI_SLV_WRSTA_DUMMY_CYCLELEN 555 #define SPIS2WSDL_S 8 //SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 556 #define SPIS2RSDL 0xFF //SPI_SLV_RDSTA_DUMMY_CYCLELEN 557 #define SPIS2RSDL_S 0 //SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 560 #define SPIS3WSCV 0xFF //SPI_SLV_WRSTA_CMD_VALUE 561 #define SPIS3WSCV_S 24 //SPI_SLV_WRSTA_CMD_VALUE_S 562 #define SPIS3RSCV 0xFF //SPI_SLV_RDSTA_CMD_VALUE 563 #define SPIS3RSCV_S 16 //SPI_SLV_RDSTA_CMD_VALUE_S 564 #define SPIS3WBCV 0xFF //SPI_SLV_WRBUF_CMD_VALUE 565 #define SPIS3WBCV_S 8 //SPI_SLV_WRBUF_CMD_VALUE_S 566 #define SPIS3RBCV 0xFF //SPI_SLV_RDBUF_CMD_VALUE 567 #define SPIS3RBCV_S 0 //SPI_SLV_RDBUF_CMD_VALUE_S 570 #define SPIE0TPPEN (1 << 31) //SPI_T_PP_ENA 571 #define SPIE0TPPS 0xF //SPI_T_PP_SHIFT 572 #define SPIE0TPPS_S 16 //SPI_T_PP_SHIFT_S 573 #define SPIE0TPPT 0xFFF //SPI_T_PP_TIME 574 #define SPIE0TPPT_S 0 //SPI_T_PP_TIME_S 577 #define SPIE1TEREN (1 << 31) //SPI_T_ERASE_ENA 578 #define SPIE1TERS 0xF //SPI_T_ERASE_SHIFT 579 #define SPIE1TERS_S 16 //SPI_T_ERASE_SHIFT_S 580 #define SPIE1TERT 0xFFF //SPI_T_ERASE_TIME 581 #define SPIE1TERT_S 0 //SPI_T_ERASE_TIME_S 584 #define SPIE2ST 0x7 //SPI_ST 585 #define SPIE2ST_S 0 //SPI_ST_S 588 #define SPIE2IHEN 0x3 //SPI_INT_HOLD_ENA 589 #define SPIE2IHEN_S 0 //SPI_INT_HOLD_ENA_S 592 #define SLCC0 ESP8266_REG(0xB00) //SLC_CONF0 593 #define SLCIR ESP8266_REG(0xB04) //SLC_INT_RAW 594 #define SLCIS ESP8266_REG(0xB08) //SLC_INT_STATUS 595 #define SLCIE ESP8266_REG(0xB0C) //SLC_INT_ENA 596 #define SLCIC ESP8266_REG(0xB10) //SLC_INT_CLR 597 #define SLCRXS ESP8266_REG(0xB14) //SLC_RX_STATUS 598 #define SLCRXP ESP8266_REG(0xB18) //SLC_RX_FIFO_PUSH 599 #define SLCTXS ESP8266_REG(0xB1C) //SLC_TX_STATUS 600 #define SLCTXP ESP8266_REG(0xB20) //SLC_TX_FIFO_POP 601 #define SLCRXL ESP8266_REG(0xB24) //SLC_RX_LINK 602 #define SLCTXL ESP8266_REG(0xB28) //SLC_TX_LINK 603 #define SLCIVTH ESP8266_REG(0xB2C) //SLC_INTVEC_TOHOST 604 #define SLCT0 ESP8266_REG(0xB30) //SLC_TOKEN0 605 #define SLCT1 ESP8266_REG(0xB34) //SLC_TOKEN1 606 #define SLCC1 ESP8266_REG(0xB38) //SLC_CONF1 607 #define SLCS0 ESP8266_REG(0xB3C) //SLC_STATE0 608 #define SLCS1 ESP8266_REG(0xB40) //SLC_STATE1 609 #define SLCBC ESP8266_REG(0xB44) //SLC_BRIDGE_CONF 610 #define SLCRXEDA ESP8266_REG(0xB48) //SLC_RX_EOF_DES_ADDR 611 #define SLCTXEDA ESP8266_REG(0xB4C) //SLC_TX_EOF_DES_ADDR 612 #define SLCRXEBDA ESP8266_REG(0xB50) //SLC_RX_EOF_BFR_DES_ADDR 613 #define SLCAT ESP8266_REG(0xB54) //SLC_AHB_TEST 614 #define SLCSS ESP8266_REG(0xB58) //SLC_SDIO_ST 615 #define SLCRXDC ESP8266_REG(0xB5C) //SLC_RX_DSCR_CONF 616 #define SLCTXD ESP8266_REG(0xB60) //SLC_TXLINK_DSCR 617 #define SLCTXDB0 ESP8266_REG(0xB64) //SLC_TXLINK_DSCR_BF0 618 #define SLCTXDB1 ESP8266_REG(0xB68) //SLC_TXLINK_DSCR_BF1 619 #define SLCRXD ESP8266_REG(0xB6C) //SLC_RXLINK_DSCR 620 #define SLCRXDB0 ESP8266_REG(0xB70) //SLC_RXLINK_DSCR_BF0 621 #define SLCRXDB1 ESP8266_REG(0xB74) //SLC_RXLINK_DSCR_BF1 622 #define SLCDT ESP8266_REG(0xB78) //SLC_DATE 623 #define SLCID ESP8266_REG(0xB7C) //SLC_ID 624 #define SLCHIR ESP8266_REG(0xB88) //SLC_HOST_INTR_RAW 625 #define SLCHC0 ESP8266_REG(0xB94) //SLC_HOST_CONF_W0 626 #define SLCHC1 ESP8266_REG(0xB98) //SLC_HOST_CONF_W1 627 #define SLCHIS ESP8266_REG(0xB9C) //SLC_HOST_INTR_ST 628 #define SLCHC2 ESP8266_REG(0xBA0) //SLC_HOST_CONF_W2 629 #define SLCHC3 ESP8266_REG(0xBA4) //SLC_HOST_CONF_W3 630 #define SLCHC4 ESP8266_REG(0xBA8) //SLC_HOST_CONF_W4 631 #define SLCHIC ESP8266_REG(0xBB0) //SLC_HOST_INTR_CLR 632 #define SLCHIE ESP8266_REG(0xBB4) //SLC_HOST_INTR_ENA 633 #define SLCHC5 ESP8266_REG(0xBBC) //SLC_HOST_CONF_W5 636 #define SLCMM (0x3) //SLC_MODE 637 #define SLCM (12) //SLC_MODE_S 638 #define SLCDTBE (1 << 9) //SLC_DATA_BURST_EN 639 #define SLCDBE (1 << 8) //SLC_DSCR_BURST_EN 640 #define SLCRXNRC (1 << 7) //SLC_RX_NO_RESTART_CLR 641 #define SLCRXAW (1 << 6) //SLC_RX_AUTO_WRBACK 642 #define SLCRXLT (1 << 5) //SLC_RX_LOOP_TEST 643 #define SLCTXLT (1 << 4) //SLC_TX_LOOP_TEST 644 #define SLCAR (1 << 3) //SLC_AHBM_RST 645 #define SLCAFR (1 << 2) //SLC_AHBM_FIFO_RST 646 #define SLCRXLR (1 << 1) //SLC_RXLINK_RST 647 #define SLCTXLR (1 << 0) //SLC_TXLINK_RST 650 #define SLCITXDE (1 << 21) //SLC_TX_DSCR_EMPTY_INT 651 #define SLCIRXDER (1 << 20) //SLC_RX_DSCR_ERR_INT 652 #define SLCITXDER (1 << 19) //SLC_TX_DSCR_ERR_INT 653 #define SLCITH (1 << 18) //SLC_TOHOST_INT 654 #define SLCIRXEOF (1 << 17) //SLC_RX_EOF_INT 655 #define SLCIRXD (1 << 16) //SLC_RX_DONE_INT 656 #define SLCITXEOF (1 << 15) //SLC_TX_EOF_INT 657 #define SLCITXD (1 << 14) //SLC_TX_DONE_INT 658 #define SLCIT0 (1 << 13) //SLC_TOKEN1_1TO0_INT 659 #define SLCIT1 (1 << 12) //SLC_TOKEN0_1TO0_INT 660 #define SLCITXO (1 << 11) //SLC_TX_OVF_INT 661 #define SLCIRXU (1 << 10) //SLC_RX_UDF_INT 662 #define SLCITXS (1 << 9) //SLC_TX_START_INT 663 #define SLCIRXS (1 << 8) //SLC_RX_START_INT 664 #define SLCIFH7 (1 << 7) //SLC_FRHOST_BIT7_INT 665 #define SLCIFH6 (1 << 6) //SLC_FRHOST_BIT6_INT 666 #define SLCIFH5 (1 << 5) //SLC_FRHOST_BIT5_INT 667 #define SLCIFH4 (1 << 4) //SLC_FRHOST_BIT4_INT 668 #define SLCIFH3 (1 << 3) //SLC_FRHOST_BIT3_INT 669 #define SLCIFH2 (1 << 2) //SLC_FRHOST_BIT2_INT 670 #define SLCIFH1 (1 << 1) //SLC_FRHOST_BIT1_INT 671 #define SLCIFH0 (1 << 0) //SLC_FRHOST_BIT0_INT 674 #define SLCRXE (1 << 1) //SLC_RX_EMPTY 675 #define SLCRXF (1 << 0) //SLC_RX_FULL 678 #define SLCTXE (1 << 1) //SLC_TX_EMPTY 679 #define SLCTXF (1 << 0) //SLC_TX_FULL 682 #define SLCRXFP (1 << 16) //SLC_RXFIFO_PUSH 683 #define SLCRXWDM (0x1FF) //SLC_RXFIFO_WDATA 684 #define SLCRXWD (0) //SLC_RXFIFO_WDATA_S 687 #define SLCTXFP (1 << 16) //SLC_TXFIFO_POP 688 #define SLCTXRDM (0x7FF) //SLC_TXFIFO_RDATA 689 #define SLCTXRD (0) //SLC_TXFIFO_RDATA_S 692 #define SLCRXLP (1 << 31) //SLC_RXLINK_PARK 693 #define SLCRXLRS (1 << 30) //SLC_RXLINK_RESTART 694 #define SLCRXLS (1 << 29) //SLC_RXLINK_START 695 #define SLCRXLE (1 << 28) //SLC_RXLINK_STOP 696 #define SLCRXLAM (0xFFFF) //SLC_RXLINK_DESCADDR_MASK 697 #define SLCRXLA (0) //SLC_RXLINK_ADDR_S 700 #define SLCTXLP (1 << 31) //SLC_TXLINK_PARK 701 #define SLCTXLRS (1 << 30) //SLC_TXLINK_RESTART 702 #define SLCTXLS (1 << 29) //SLC_TXLINK_START 703 #define SLCTXLE (1 << 28) //SLC_TXLINK_STOP 704 #define SLCTXLAM (0xFFFF) //SLC_TXLINK_DESCADDR_MASK 705 #define SLCTXLA (0) //SLC_TXLINK_ADDR_S 708 #define SLCTM (0xFFF) //SLC_TOKENx_MASK 709 #define SLCTT (16) //SLC_TOKENx_S 710 #define SLCTIM (1 << 14) //SLC_TOKENx_LOCAL_INC_MORE 711 #define SLCTI (1 << 13) //SLC_TOKENx_LOCAL_INC 712 #define SLCTW (1 << 12) //SLC_TOKENx_LOCAL_WR 713 #define SLCTDM (0xFFF) //SLC_TOKENx_LOCAL_WDATA 714 #define SLCTD (0) //SLC_TOKENx_LOCAL_WDATA_S 717 #define SLCBFMEM (0xF) //SLC_FIFO_MAP_ENA 718 #define SLCBFME (8) //SLC_FIFO_MAP_ENA_S 719 #define SLCBTEEM (0x3F) //SLC_TXEOF_ENA 720 #define SLCBTEE (0) //SLC_TXEOF_ENA_S 723 #define SLCATAM (0x3) //SLC_AHB_TESTADDR 724 #define SLCATA (4) //SLC_AHB_TESTADDR_S 725 #define SLCATMM (0x7) //SLC_AHB_TESTMODE 726 #define SLCATM (0) //SLC_AHB_TESTMODE_S 729 #define SLCSBM (0x7) //SLC_BUS_ST 730 #define SLCSB (12) //SLC_BUS_ST_S 731 #define SLCSW (1 << 8) //SLC_SDIO_WAKEUP 732 #define SLCSFM (0xF) //SLC_FUNC_ST 733 #define SLCSF (4) //SLC_FUNC_ST_S 734 #define SLCSCM (0x7) //SLC_CMD_ST 735 #define SLCSC (0) //SLC_CMD_ST_S 738 #define SLCBRXFE (1 << 20) //SLC_RX_FILL_EN 739 #define SLCBRXEM (1 << 19) //SLC_RX_EOF_MODE 740 #define SLCBRXFM (1 << 18) //SLC_RX_FILL_MODE 741 #define SLCBINR (1 << 17) //SLC_INFOR_NO_REPLACE 742 #define SLCBTNR (1 << 16) //SLC_TOKEN_NO_REPLACE 743 #define SLCBPICM (0xFFFF) //SLC_POP_IDLE_CNT 744 #define SLCBPIC (0) //SLC_POP_IDLE_CNT_S 747 #define i2c_bbpll 0x67 748 #define i2c_bbpll_hostid 4 749 #define i2c_bbpll_en_audio_clock_out 4 750 #define i2c_bbpll_en_audio_clock_out_msb 7 751 #define i2c_bbpll_en_audio_clock_out_lsb 7 752 #define I2S_CLK_ENABLE() i2c_writeReg_Mask_def(i2c_bbpll, i2c_bbpll_en_audio_clock_out, 1) 753 #define I2SBASEFREQ (160000000L) 755 #define I2STXF ESP8266_REG(0xe00) //I2STXFIFO (32bit) 756 #define I2SRXF ESP8266_REG(0xe04) //I2SRXFIFO (32bit) 757 #define I2SC ESP8266_REG(0xe08) //I2SCONF 758 #define I2SIR ESP8266_REG(0xe0C) //I2SINT_RAW 759 #define I2SIS ESP8266_REG(0xe10) //I2SINT_ST 760 #define I2SIE ESP8266_REG(0xe14) //I2SINT_ENA 761 #define I2SIC ESP8266_REG(0xe18) //I2SINT_CLR 762 #define I2ST ESP8266_REG(0xe1C) //I2STIMING 763 #define I2SFC ESP8266_REG(0xe20) //I2S_FIFO_CONF 764 #define I2SRXEN ESP8266_REG(0xe24) //I2SRXEOF_NUM (32bit) 765 #define I2SCSD ESP8266_REG(0xe28) //I2SCONF_SIGLE_DATA (32bit) 766 #define I2SCC ESP8266_REG(0xe2C) //I2SCONF_CHAN 769 #define I2SBDM (0x3F) //I2S_BCK_DIV_NUM 770 #define I2SBD (22) //I2S_BCK_DIV_NUM_S 771 #define I2SCDM (0x3F) //I2S_CLKM_DIV_NUM 772 #define I2SCD (16) //I2S_CLKM_DIV_NUM_S 773 #define I2SBMM (0xF) //I2S_BITS_MOD 774 #define I2SBM (12) //I2S_BITS_MOD_S 775 #define I2SRMS (1 << 11) //I2S_RECE_MSB_SHIFT 776 #define I2STMS (1 << 10) //I2S_TRANS_MSB_SHIFT 777 #define I2SRXS (1 << 9) //I2S_I2S_RX_START 778 #define I2STXS (1 << 8) //I2S_I2S_TX_START 779 #define I2SMR (1 << 7) //I2S_MSB_RIGHT 780 #define I2SRF (1 << 6) //I2S_RIGHT_FIRST 781 #define I2SRSM (1 << 5) //I2S_RECE_SLAVE_MOD 782 #define I2STSM (1 << 4) //I2S_TRANS_SLAVE_MOD 783 #define I2SRXFR (1 << 3) //I2S_I2S_RX_FIFO_RESET 784 #define I2STXFR (1 << 2) //I2S_I2S_TX_FIFO_RESET 785 #define I2SRXR (1 << 1) //I2S_I2S_RX_RESET 786 #define I2STXR (1 << 0) //I2S_I2S_TX_RESET 787 #define I2SRST (0xF) //I2S_I2S_RESET_MASK 790 #define I2SITXRE (1 << 5) //I2S_I2S_TX_REMPTY_INT 791 #define I2SITXWF (1 << 4) //I2S_I2S_TX_WFULL_INT 792 #define I2SIRXRE (1 << 3) //I2S_I2S_RX_REMPTY_INT 793 #define I2SIRXWF (1 << 2) //I2S_I2S_RX_WFULL_INT 794 #define I2SITXPD (1 << 1) //I2S_I2S_TX_PUT_DATA_INT 795 #define I2SIRXTD (1 << 0) //I2S_I2S_RX_TAKE_DATA_INT 798 #define I2STBII (1 << 22) //I2S_TRANS_BCK_IN_INV 799 #define I2SRDS (1 << 21) //I2S_RECE_DSYNC_SW 800 #define I2STDS (1 << 20) //I2S_TRANS_DSYNC_SW 801 #define I2SRBODM (0x3) //I2S_RECE_BCK_OUT_DELAY 802 #define I2SRBOD (18) //I2S_RECE_BCK_OUT_DELAY_S 803 #define I2SRWODM (0x3) //I2S_RECE_WS_OUT_DELAY 804 #define I2SRWOD (16) //I2S_RECE_WS_OUT_DELAY_S 805 #define I2STSODM (0x3) //I2S_TRANS_SD_OUT_DELAY 806 #define I2STSOD (14) //I2S_TRANS_SD_OUT_DELAY_S 807 #define I2STWODM (0x3) //I2S_TRANS_WS_OUT_DELAY 808 #define I2STWOD (12) //I2S_TRANS_WS_OUT_DELAY_S 809 #define I2STBODM (0x3) //I2S_TRANS_BCK_OUT_DELAY 810 #define I2STBOD (10) //I2S_TRANS_BCK_OUT_DELAY_S 811 #define I2SRSIDM (0x3) //I2S_RECE_SD_IN_DELAY 812 #define I2SRSID (8) //I2S_RECE_SD_IN_DELAY_S 813 #define I2SRWIDM (0x3) //I2S_RECE_WS_IN_DELAY 814 #define I2SRWID (6) //I2S_RECE_WS_IN_DELAY_S 815 #define I2SRBIDM (0x3) //I2S_RECE_BCK_IN_DELAY 816 #define I2SRBID (4) //I2S_RECE_BCK_IN_DELAY_S 817 #define I2STWIDM (0x3) //I2S_TRANS_WS_IN_DELAY 818 #define I2STWID (2) //I2S_TRANS_WS_IN_DELAY_S 819 #define I2STBIDM (0x3) //I2S_TRANS_BCK_IN_DELAY 820 #define I2STBID (0) //I2S_TRANS_BCK_IN_DELAY_S 823 #define I2SRXFMM (0x7) //I2S_I2S_RX_FIFO_MOD 824 #define I2SRXFM (16) //I2S_I2S_RX_FIFO_MOD_S 825 #define I2STXFMM (0x7) //I2S_I2S_TX_FIFO_MOD 826 #define I2STXFM (13) //I2S_I2S_TX_FIFO_MOD_S 827 #define I2SDE (1 << 12) //I2S_I2S_DSCR_EN 828 #define I2STXDNM (0x3F) //I2S_I2S_TX_DATA_NUM 829 #define I2STXDN (6) //I2S_I2S_TX_DATA_NUM_S 830 #define I2SRXDNM (0x3F) //I2S_I2S_RX_DATA_NUM 831 #define I2SRXDN (0) //I2S_I2S_RX_DATA_NUM_S 834 #define I2SRXCMM (0x3) //I2S_RX_CHAN_MOD 835 #define I2SRXCM (3) //I2S_RX_CHAN_MOD_S 836 #define I2STXCMM (0x7) //I2S_TX_CHAN_MOD 837 #define I2STXCM (0) //I2S_TX_CHAN_MOD_S 843 #define RANDOM_REG32 ESP8266_DREG(0x20E44) const uint8_t esp8266_gpioToFn[16]