Structure to manage low-level adjustment of PHY data Does not contain the data but a reference to it. The data should not be accessed directly. More...

#include <esp_phy.h>

Collaboration diagram for PhyInitData:

Public Types

using txpwr_index_t = uint8_t
 Index for configurable power level, from 0-5. See PhyInitData::set_txpwr_dqb. More...
 

Public Member Functions

uint8_t get_version () const
 PHY data version number. Currently version 8. More...
 
void undocumented_26_29 ()
 Ordinal 26-29. More...
 
void set_power_limits (txpwr_index_t chan1, txpwr_index_t chan11, txpwr_index_t chan13, txpwr_index_t chan14)
 Configure the maximum TX powers for channels 1, 11, 13 and 14. More...
 
void disable_power_limits ()
 Disable power limits on channels 1, 11, 13 and 14. More...
 
void set_txpwr_dqb (txpwr_index_t level, uint8_t value)
 Set TX power level. TX power can be switched between six levels. Level 0 represents the maximum TX power, level 5 the minimum. More...
 
void set_txpwr (uint8_t mcs_index, txpwr_index_t txpwr_qdb)
 Select target power level for specific data rate according to Modulation Coding Scheme (MCS) More...
 
void set_crystal_freq (uint8_t value=1)
 Select crystal frequency. More...
 
void set_sdio_configure (uint8_t value=0)
 Configure SDIO behaviour. More...
 
void set_bt_configure (uint8_t value=0)
 Configure bluetooth. More...
 
void set_bt_protocol (uint8_t value=0)
 Configure Bluetooth protocol. More...
 
void set_dual_ant_configure (uint8_t value=0)
 Configure dual antenna arrangement. More...
 
void set_share_xtal (uint8_t value=0)
 Set Crystal state during sleep mode This option is to share crystal clock for BT. More...
 
void undocumented_64_73 ()
 Ordinal 64-73. More...
 
void set_low_power_en (uint8_t value=0)
 Configure low-power mode. More...
 
void set_lp_rf_stg10 (uint8_t value=0)
 Set attenuation of RF gain stage 0 and 1. More...
 
void set_lp_bb_att_ext (uint8_t value=0)
 Set attenuation of BB gain. More...
 
void set_default_power_limits_11b ()
 Set power limits for 802.11b to default, which is same as MCS0 and 6Mbits/s modes. See PhyInitData::set_txpwr. More...
 
void set_power_limits_11b (txpwr_index_t txpwr_index_11b_0, txpwr_index_t txpwr_index_11b_1)
 Configure 802.11b power limits. More...
 
void set_vdd33_const (uint8_t value=33)
 Set PA_VDD voltage. More...
 
void set_rf_cal_disable (uint8_t value=0)
 Disable RF calibration for certain number of times. More...
 
void set_freq_correct (uint8_t bbpll=3, int8_t force_freq_offset=0)
 Enable frequency correction. More...
 
void set_rf_calibration (uint8_t value=1)
 RF_calibration. More...
 

Public Attributes

uint8_t * data
 

Detailed Description

Structure to manage low-level adjustment of PHY data Does not contain the data but a reference to it. The data should not be accessed directly.

See also
For further details, see the following PDF documents:
  • ESP8266 Phy Init Bin Parameter Configuration Guide
  • ESP8266 Non-OS SDK API Reference (Final version is version 4)

Member Typedef Documentation

◆ txpwr_index_t

using PhyInitData::txpwr_index_t = uint8_t

Index for configurable power level, from 0-5. See PhyInitData::set_txpwr_dqb.

Member Function Documentation

◆ disable_power_limits()

void PhyInitData::disable_power_limits ( )
inline

Disable power limits on channels 1, 11, 13 and 14.

◆ get_version()

uint8_t PhyInitData::get_version ( ) const
inline

PHY data version number. Currently version 8.

◆ set_bt_configure()

void PhyInitData::set_bt_configure ( uint8_t  value = 0)
inline

Configure bluetooth.

Parameters
valueValues are:
  • 0: None,no bluetooth
  • 1: Enable, pins are:
    • GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI
    • MTMS -> BT_ACTIVE
    • MTCK -> BT_PRIORITY
    • U0RXD -> ANT_SEL_BT
  • 2: None, have bluetooth
  • 3: Enable, pins are:
    • GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI
    • MTMS -> BT_PRIORITY
    • MTCK -> BT_ACTIVE
    • U0RXD -> ANT_SEL_BT

◆ set_bt_protocol()

void PhyInitData::set_bt_protocol ( uint8_t  value = 0)
inline

Configure Bluetooth protocol.

Parameters
valueValues are:
  • 0: WiFi-BT are not enabled. Antenna is for WiFi
  • 1: WiFi-BT are not enabled. Antenna is for BT
  • 2: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), independent ant
  • 3: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), independent ant
  • 4: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), share ant
  • 5: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), share ant

◆ set_crystal_freq()

void PhyInitData::set_crystal_freq ( uint8_t  value = 1)
inline

Select crystal frequency.

Parameters
valueValues are:
  • 0: 40MHz
  • 1: 26MHz
  • 2: 24MHz

◆ set_default_power_limits_11b()

void PhyInitData::set_default_power_limits_11b ( )
inline

Set power limits for 802.11b to default, which is same as MCS0 and 6Mbits/s modes. See PhyInitData::set_txpwr.

◆ set_dual_ant_configure()

void PhyInitData::set_dual_ant_configure ( uint8_t  value = 0)
inline

Configure dual antenna arrangement.

Parameters
valueValues are:
  • 0: None
  • 1: dual_ant (antenna diversity for WiFi-only): GPIO0 + U0RXD
  • 2: T/R switch for External PA/LNA: GPIO0 is high and U0RXD is low during Tx
  • 3: T/R switch for External PA/LNA: GPIO0 is low and U0RXD is high during Tx

◆ set_freq_correct()

void PhyInitData::set_freq_correct ( uint8_t  bbpll = 3,
int8_t  force_freq_offset = 0 
)
inline

Enable frequency correction.

Parameters
modeCorrection mode:
  • 0x00: do not correct frequency offset
  • 0x01: auto-correct, bbpll 168M, can correct positive and negative offsets
  • 0x03: auto-correct, bbpll 160M, can only correct positive offsets
  • 0x05: Correct using force_freq_offset, bbpll 168M, offset can be any value
  • 0x07: Correct using force_freq_offset, bbpll 160M, offset must >= 0
force_freq_offsetCorrection figure in 8kHz steps, signed

Bits are defined as follows:

  • bit 0
    • 0: do not correct frequency offset
    • 1: correct frequency offset
  • bit 1
    • 0: bbpll is 168M, it can correct + and - frequency offset
    • 1: bbpll is 160M, it only can correct + frequency offset
  • bit 2
    • 0: auto measure frequency offset and correct it
    • 1: use force_freq_offset to correct frequency offset

◆ set_low_power_en()

void PhyInitData::set_low_power_en ( uint8_t  value = 0)
inline

Configure low-power mode.

Parameters
valueValues are:
  • 0: disable low power mode
  • 1: enable low power mode

◆ set_lp_bb_att_ext()

void PhyInitData::set_lp_bb_att_ext ( uint8_t  value = 0)
inline

Set attenuation of BB gain.

Parameters
valueAttenuation in 0.25dB steps. Max valve is 24 (-6dB):
  • 0: 0dB
  • 1: -0.25dB
  • 2: -0.5dB
  • 3: -0.75dB
  • 4: -1dB
  • 5: -1.25dB
  • 6: -1.5dB
  • 7: -1.75dB
  • 8: -2dB etc.

◆ set_lp_rf_stg10()

void PhyInitData::set_lp_rf_stg10 ( uint8_t  value = 0)
inline

Set attenuation of RF gain stage 0 and 1.

Parameters
valueValues are:
  • 0x0f: 0dB
  • 0x0e: -2.5dB
  • 0x0d: -6dB
  • 0x09: -8.5dB
  • 0x0c: -11.5dB
  • 0x08: -14dB
  • 0x04: -17.5dB
  • 0x00: -23dB

◆ set_power_limits()

void PhyInitData::set_power_limits ( txpwr_index_t  chan1,
txpwr_index_t  chan11,
txpwr_index_t  chan13,
txpwr_index_t  chan14 
)
inline

Configure the maximum TX powers for channels 1, 11, 13 and 14.

Parameters
chan1Limit for channel 1
chan11Limit for channel 11
chan13Limit for channel 13
chan14Limit for channel 14

◆ set_power_limits_11b()

void PhyInitData::set_power_limits_11b ( txpwr_index_t  txpwr_index_11b_0,
txpwr_index_t  txpwr_index_11b_1 
)
inline

Configure 802.11b power limits.

Parameters
txpwr_index_11b_0Power level for 1Mbit/s and 2Mbit/s modes
txpwr_index_11b_1Power level for 5.5Mbits/s and 11Mbits/s modes

◆ set_rf_cal_disable()

void PhyInitData::set_rf_cal_disable ( uint8_t  value = 0)
inline

Disable RF calibration for certain number of times.

Parameters
valueNumber of times to disable RF calibration
See also
See ESP8266 Non-OS SDK API Reference:
  • system_deep_sleep_set_option
  • system_phy_set_rfoption

◆ set_rf_calibration()

void PhyInitData::set_rf_calibration ( uint8_t  value = 1)
inline

RF_calibration.

Parameters
valueValues are:
  • 0: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init
  • 1: RF init only do TX power control CAL, others using RF CAL data in flash, it takes about 20ms for RF init
  • 2: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init (same as 0?!)
  • 3: RF init do all RF CAL, it takes about 200ms for RF init
Note
To ensure better RF performance, it is recommend to set RF_calibration to 3, otherwise the RF performance may become poor.
See also
See ESP8266 Non-OS SDK API Reference:
  • system_phy_set_powerup_option

◆ set_sdio_configure()

void PhyInitData::set_sdio_configure ( uint8_t  value = 0)
inline

Configure SDIO behaviour.

Parameters
valueValues are:
  • 0: Auto by pin strapping
  • 1: SDIO data output is at negative edges (SDIO V1.1)
  • 2: SDIO data output is at positive edges (SDIO V2.0)

◆ set_share_xtal()

void PhyInitData::set_share_xtal ( uint8_t  value = 0)
inline

Set Crystal state during sleep mode This option is to share crystal clock for BT.

Parameters
valueThe state of Crystal during sleeping:
  • 0: Off
  • 1: Forcibly On
  • 2: Automatically On according to XPD_DCDC
  • 3: Automatically On according to GPIO2

◆ set_txpwr()

void PhyInitData::set_txpwr ( uint8_t  mcs_index,
txpwr_index_t  txpwr_qdb 
)
inline

Select target power level for specific data rate according to Modulation Coding Scheme (MCS)

Parameters
mcs_indexModulation Coding Scheme (MCS) index, from 0-7
txpwr_qdbPower level 0-5. See PhyInitData::set_txpwr_dqb.
Note
The defaults are:
  • MCS0: qdb_0 1 Mbit/s, 2 Mbit/s, 5.5 Mbit/s, 11 Mbit/s, 6 Mbit/s, 9 Mbit/s)
  • MCS1: qdb_0 12 Mbit/s)
  • MCS2: qdb_1 18 Mbit/s)
  • MCS3: qdb_1 24 Mbit/s
  • MCS4: qdb_2 36 Mbit/s
  • MCS5: qdb_3 48 Mbit/s
  • MCS6: qdb_4 54 Mbit/s
  • MCS7: qdb_5

◆ set_txpwr_dqb()

void PhyInitData::set_txpwr_dqb ( txpwr_index_t  level,
uint8_t  value 
)
inline

Set TX power level. TX power can be switched between six levels. Level 0 represents the maximum TX power, level 5 the minimum.

Parameters
levelIndex from 0-5
valuePower level in 0.25dB increments
Note
Defaults are:
  • 0: 78/4 = 19.5dBm
  • 1: 74/4 = 18.5dBm
  • 2: 70/4 = 17.5dBm
  • 3: 64/4 = 16dBm
  • 4: 60/4 = 15dBm
  • 5: 56/4 = 14dBm
See also
See ESP8266 Non-OS SDK API Reference:
  • system_phy_set_max_tpw

◆ set_vdd33_const()

void PhyInitData::set_vdd33_const ( uint8_t  value = 33)
inline

Set PA_VDD voltage.

Parameters
valueValues are:
  • 0xff: Can measure VDD33
  • 18 <= value <= 36: use input voltage, where value = voltage * 10, so 33 is 3.3V, 30 is 3.0V, etc.
  • value < 18, value > 36: default voltage is 3.3V

The value of this byte depends on the TOUT pin usage:

  • analogRead function: system_adc_read()
    • Only available when wire TOUT pin 17 to external circuitry, Input Voltage Range restricted to 0 ~ 1.0V.
      • For this function the vdd33_const must be set as real power voltage of VDD3P3 pin 3 and 4
      • The range of operating voltage of ESP8266 is 1.8V ~ 3.6V, the unit of vdd33_const is 0.1V, so effective value range of vdd33_const is [18, 36].
  • getVcc function: system_get_vdd33()
    • Only available when TOUT pin 17 is suspended (floating), this function measure the power voltage of VDD3P3 pin 3 and 4
    • For this function the vdd33_const must be set to 255 (0xFF).
See also
See ESP8266 Non-OS SDK API Reference:
  • system_get_vdd33
  • system_adc_read
  • system_adc_read_fast

◆ undocumented_26_29()

void PhyInitData::undocumented_26_29 ( )
inline

Ordinal 26-29.

These values are poorly defined.

  • [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div
  • [27] = 10, // spur_freq_cfg_div

Each bit for 1 channel, 1 to select the spur_freq if in band, else 40

  • [28] = 0xff, // spur_freq_en_h
  • [29] = 0xff, // spur_freq_en_l

◆ undocumented_64_73()

void PhyInitData::undocumented_64_73 ( )
inline

Ordinal 64-73.

These values are poorly defined.

  • [64] = 225, // spur_freq_cfg_2, spur_freq_2=spur_freq_cfg_2/spur_freq_cfg_div_2
  • [65] = 10, // spur_freq_cfg_div_2
  • [66] = 0, // spur_freq_en_h_2
  • [67] = 0, // spur_freq_en_l_2
  • [68] = 0, // spur_freq_cfg_msb
  • [69] = 0, // spur_freq_cfg_2_msb
  • [70] = 0, // spur_freq_cfg_3_low
  • [71] = 0, // spur_freq_cfg_3_high
  • [72] = 0, // spur_freq_cfg_4_low
  • [73] = 0, // spur_freq_cfg_4_high

Member Data Documentation

◆ data

uint8_t* PhyInitData::data

The documentation for this struct was generated from the following file: